Understanding spider monkey disassemble

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Kyoungjoo1
Posts: 1
Joined: November 11th, 2014, 2:40 am

Understanding spider monkey disassemble

Post by Kyoungjoo1 »

Hi, this is disassemble for function f()
var b = 11;
function f(t) {
var h;
h = t*110
for(var i = 0 ; i < 10000; ++i)
b+=h;
return h;
}
for(var i = 0 ; i < 100; ++i)
f(i);

I found mull operation assemble code and find point where for loop condition checks(at address 0xb6fbe3c8). Help me understand why there are lot of code between this 2 addresses and what they do. And also where is loop ??? I hope someone will help me. Thanks

0xb6fbe0bc: mov r12, #110 ; 0x6e

0xb6fbe0c0: smull r2, r12, r1, r12
0xb6fbe0c4: cmp r12, r2, asr #31
0xb6fbe0c8: ldrne pc, [pc, #12] ; 0xb6fbe0dc
0xb6fbe0cc: mov r0, #0
0xb6fbe0d0: b 0xb6fbe2f0
0xb6fbe0d4: b 0xb6fbe0e0
0xb6fbe0d8: ; <UNDEFINED> instruction: 0xffff0002
0xb6fbe0dc: ldrbtlt pc, [r12], r8, ror #5 ; <UNPREDICTABLE>
0xb6fbe0e0: sub sp, sp, #128 ; 0x80
0xb6fbe0e4: mvn r1, #125 ; 0x7d
0xb6fbe0e8: mov r0, #0
0xb6fbe0ec: ldr lr, [r3, #-4]
0xb6fbe0f0: tst lr, #1
0xb6fbe0f4: beq 0xb6fbe0fc
0xb6fbe0f8: ldrd r0, [r3, #-36] ; 0xffffffdc
0xb6fbe0fc: push {r2} ; (str r2, [sp, #-4]!)
0xb6fbe100: push {r3} ; (str r3, [sp, #-4]!)
0xb6fbe104: movw r2, #65535 ; 0xffff
0xb6fbe108: movt r2, #65535 ; 0xffff
0xb6fbe10c: ldr lr, [r2, #144] ; 0x90
0xb6fbe110: cmp lr, #0
0xb6fbe114: bne 0xb6fbe17c
0xb6fbe118: push {r0, r1, r2, r3}
0xb6fbe11c: vpush {s0-s15}
0xb6fbe120: push {r1} ; (str r1, [sp, #-4]!)
0xb6fbe124: push {r0} ; (str r0, [sp, #-4]!)
0xb6fbe128: mov r2, sp
0xb6fbe12c: mov r3, sp
0xb6fbe130: bic sp, sp, #7
0xb6fbe134: push {r3} ; (str r3, [sp, #-4]!)
0xb6fbe138: movw r12, #23956 ; 0x5d94
0xb6fbe13c: movt r12, #317 ; 0x13d
0xb6fbe140: ldr r3, [r12]
0xb6fbe144: sub sp, sp, #4
0xb6fbe168: ldr sp, [sp]
0xb6fbe16c: pop {r0} ; (ldr r0, [sp], #4)
0xb6fbe170: pop {r1} ; (ldr r1, [sp], #4)
0xb6fbe174: vpop {s0-s15}
0xb6fbe178: pop {r0, r1, r2, r3}
0xb6fbe17c: pop {r3} ; (ldr r3, [sp], #4)
0xb6fbe180: pop {r2} ; (ldr r2, [sp], #4)
0xb6fbe184: ldrd r0, [r3, #-52] ; 0xffffffcc
0xb6fbe188: push {r2} ; (str r2, [sp, #-4]!)
0xb6fbe18c: push {r3} ; (str r3, [sp, #-4]!)
0xb6fbe190: movw r2, #65535 ; 0xffff
0xb6fbe194: movt r2, #65535 ; 0xffff
0xb6fbe198: ldr lr, [r2, #144] ; 0x90
0xb6fbe19c: cmp lr, #0
0xb6fbe1a0: bne 0xb6fbe208
0xb6fbe1a4: push {r0, r1, r2, r3}
0xb6fbe1a8: vpush {s0-s15}
0xb6fbe1ac: push {r1} ; (str r1, [sp, #-4]!)
0xb6fbe1b0: push {r0} ; (str r0, [sp, #-4]!)
0xb6fbe1b4: mov r2, sp
0xb6fbe1b8: mov r3, sp
0xb6fbe1bc: bic sp, sp, #7
0xb6fbe1c0: push {r3} ; (str r3, [sp, #-4]!)
0xb6fbe1c4: movw r12, #23956 ; 0x5d94
0xb6fbe1c8: movt r12, #317 ; 0x13d
0xb6fbe1cc: ldr r3, [r12]
0xb6fbe1d0: sub sp, sp, #4
0xb6fbe1d4: mov r1, r2
0xb6fbe1d8: mov r0, r3
0xb6fbe1dc: tst sp, #7
0xb6fbe1e0: ldrne r12, [r12, -r12]
0xb6fbe1e4: movw r12, #50925 ; 0xc6ed
0xb6fbe1e8: movt r12, #68 ; 0x44
0xb6fbe1ec: blx r12
0xb6fbe1f0: add sp, sp, #4
0xb6fbe1f4: ldr sp, [sp]
0xb6fbe1f8: pop {r0} ; (ldr r0, [sp], #4)
0xb6fbe1fc: pop {r1} ; (ldr r1, [sp], #4)
0xb6fbe200: vpop {s0-s15}
0xb6fbe204: pop {r0, r1, r2, r3}
0xb6fbe208: pop {r3} ; (ldr r3, [sp], #4)
0xb6fbe20c: pop {r2} ; (ldr r2, [sp], #4)
0xb6fbe210: ldr r2, [r3, #-60] ; 0x3c
0xb6fbe214: ldr r4, [r3, #-56] ; 0x38
0xb6fbe218: push {r0} ; (str r0, [sp, #-4]!)
0xb6fbe21c: push {r1} ; (str r1, [sp, #-4]!)
0xb6fbe220: movw r0, #65535 ; 0xffff
0xb6fbe224: movt r0, #65535 ; 0xffff
0xb6fbe228: ldr lr, [r0, #144] ; 0x90
0xb6fbe22c: cmp lr, #0
0xb6fbe230: bne 0xb6fbe2a4
0xb6fbe234: push {r0, r1, r2, r3}
0xb6fbe238: vpush {s0-s15}
0xb6fbe23c: push {r4} ; (str r4, [sp, #-4]!)
0xb6fbe240: push {r2} ; (str r2, [sp, #-4]!)
0xb6fbe244: mov r0, sp
0xb6fbe248: mov r1, sp
0xb6fbe24c: bic sp, sp, #7
0xb6fbe250: push {r1} ; (str r1, [sp, #-4]!)
0xb6fbe254: movw r12, #23956 ; 0x5d94
0xb6fbe258: movt r12, #317 ; 0x13d
0xb6fbe25c: ldr r1, [r12]
0xb6fbe260: sub sp, sp, #4
0xb6fbe264: sub sp, sp, #8
0xb6fbe268: str r0, [sp]
0xb6fbe26c: mov r0, r1
0xb6fbe270: ldr r1, [sp]
0xb6fbe274: add sp, sp, #8
0xb6fbe278: tst sp, #7
0xb6fbe27c: ldrne r12, [r12, -r12]
0xb6fbe280: movw r12, #50925 ; 0xc6ed
0xb6fbe284: movt r12, #68 ; 0x44
0xb6fbe288: blx r12
0xb6fbe28c: add sp, sp, #4
0xb6fbe290: ldr sp, [sp]
0xb6fbe294: pop {r2} ; (ldr r2, [sp], #4)
0xb6fbe298: pop {r4} ; (ldr r4, [sp], #4)
0xb6fbe29c: vpop {s0-s15}
0xb6fbe2a0: pop {r0, r1, r2, r3}
0xb6fbe2a4: pop {r1} ; (ldr r1, [sp], #4)
0xb6fbe2a8: pop {r0} ; (ldr r0, [sp], #4)
0xb6fbe2ac: ldr r5, [sp, #144] ; 0x90
0xb6fbe2b0: ldr r3, [sp, #148] ; 0x94
0xb6fbe2b4: cmn r3, #126 ; 0x7e
0xb6fbe2b8: bne 0xb6fbe4a0
0xb6fbe2bc: ldr r7, [sp, #152] ; 0x98
0xb6fbe2c0: ldr r6, [sp, #156] ; 0x9c
0xb6fbe2c4: cmn r6, #127 ; 0x7f
0xb6fbe2c8: ldrne pc, [pc, #296] ; 0xb6fbe3f8
0xb6fbe2cc: mov r8, r0
0xb6fbe2d0: cmn r1, #127 ; 0x7f
0xb6fbe2d4: ldrne pc, [pc, #288] ; 0xb6fbe3fc
0xb6fbe2d8: mov r9, r2
0xb6fbe2dc: cmn r4, #127 ; 0x7f
0xb6fbe2e0: ldrne pc, [pc, #280] ; 0xb6fbe400
0xb6fbe2e4: mov r0, r9
0xb6fbe2e8: mov r2, r8
0xb6fbe2ec: mov r1, r7
0xb6fbe2f0: movw r3, #16448 ; 0x4040
0xb6fbe2f4: movt r3, #46290 ; 0xb4d2
0xb6fbe2f8: push {r0} ; (str r0, [sp, #-4]!)
0xb6fbe2fc: movw r0, #65535 ; 0xffff
0xb6fbe300: movt r0, #65535 ; 0xffff
0xb6fbe304: ldr lr, [r0, #144] ; 0x90
0xb6fbe308: cmp lr, #0
0xb6fbe30c: bne 0xb6fbe3b8
0xb6fbe310: movw r12, #16448 ; 0x4040
0xb6fbe314: movt r12, #46290 ; 0xb4d2
0xb6fbe318: cmp r3, r12
0xb6fbe31c: bne 0xb6fbe324
0xb6fbe320: b 0xb6fbe36c
0xb6fbe324: push {r0, r1, r2, r3}
0xb6fbe328: vpush {s0-s15}
0xb6fbe32c: mov r0, sp
0xb6fbe330: bic sp, sp, #7
0xb6fbe334: push {r0} ; (str r0, [sp, #-4]!)
0xb6fbe338: movw r0, #23360 ; 0x5b40
0xb6fbe33c: movt r0, #141 ; 0x8d
0xb6fbe340: sub sp, sp, #4
0xb6fbe344: tst sp, #7
0xb6fbe348: ldrne r12, [r12, -r12]
0xb6fbe34c: movw r12, #55157 ; 0xd775
0xb6fbe350: movt r12, #52 ; 0x34
0xb6fbe354: blx r12
0xb6fbe358: add sp, sp, #4
0xb6fbe35c: ldr sp, [sp]
0xb6fbe360: vpop {s0-s15}
0xb6fbe364: pop {r0, r1, r2, r3}
0xb6fbe368: bkpt 0x000e
0xb6fbe36c: push {r0, r1, r2, r3}
0xb6fbe370: vpush {s0-s15}
0xb6fbe374: mov r0, sp
0xb6fbe378: bic sp, sp, #7
0xb6fbe37c: push {r0} ; (str r0, [sp, #-4]!)
0xb6fbe380: movw r12, #23956 ; 0x5d94
0xb6fbe384: movt r12, #317 ; 0x13d
0xb6fbe388: ldr r0, [r12]
0xb6fbe38c: sub sp, sp, #4
0xb6fbe390: mov r1, r3
0xb6fbe394: tst sp, #7
0xb6fbe398: ldrne r12, [r12, -r12]
0xb6fbe39c: movw r12, #49081 ; 0xbfb9
0xb6fbe3a0: movt r12, #68 ; 0x44
0xb6fbe3a4: blx r12
0xb6fbe3a8: add sp, sp, #4
0xb6fbe3ac: ldr sp, [sp]
0xb6fbe3b0: vpop {s0-s15}
0xb6fbe3b4: pop {r0, r1, r2, r3}
0xb6fbe3b8: pop {r0} ; (ldr r0, [sp], #4)
0xb6fbe3bc: ldr r3, [r3, #8]

0xb6fbe3c0: movw r12, #10000 ; 0x2710
0xb6fbe3c4: cmp r0, r12
0xb6fbe3c8: bge 0xb6fbe3e4
0xb6fbe3cc: ldr r4, [r3, #2560] ; 0xa00
0xb6fbe3d0: adds r5, r4, #1
0xb6fbe3d4: ldrvs pc, [pc, #40] ; 0xb6fbe404
0xb6fbe3d8: str r5, [r3, #2560] ; 0xa00
0xb6fbe3dc: adds r0, r0, #1
0xb6fbe3e0: b 0xb6fbe3e4
0xb6fbe3e4: mvn r3, #126 ; 0x7e
0xb6fbe3e8: add sp, sp, #128 ; 0x80
0xb6fbe3ec: pop {pc} ; (ldr pc, [sp], #4)
0xb6fbe3f0: b 0xb6fbe40c
0xb6fbe3f4: ; <UNDEFINED> instruction: 0xffff0006
0xb6fbe3f8: ldrbtlt pc, [r12], r12, ror #5 ; <UNPREDICTABLE>
0xb6fbe3fc: ; <UNDEFINED> instruction: 0xb6fcf2f0
0xb6fbe400: ; <UNDEFINED> instruction: 0xb6fcf2f4
0xb6fbe404: ; <UNDEFINED> instruction: 0xb6fcf2f8
0xb6fbe408: cdple 14, 10, cr11, cr13, cr15, {7}
0xb6fbe40c: nop {0}
0xb6fbe410: push {lr} ; (str lr, [sp, #-4]!)
0xb6fbe414: movw r12, #65535 ; 0xffff
....
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